1. Field of the Invention
The present invention relates to solid-state imaging devices, and particularly relates to a high-pixel-density solid-state imaging device that enables expansion of a dynamic range, a high-speed shutter, and a decreased drive voltage.
2. Description of the Related Art
At present, solid-state imaging devices, such as charge-coupled devices (CCDs) and complementary metal-oxide semiconductor (CMOS) devices, are widely used in video cameras, still cameras, and the like. A higher pixel density is demanded for enhancing the performance of solid-state imaging devices, for example, realizing a higher resolution. Also, an improvement in function, such as a high-speed shutter and expansion of a dynamic range, and a lower driving power for reducing power consumption are demanded.
Hereinafter, the structure and operation of a solid-state imaging device according to a related art will be described (for example, International Publication No. 2009/034623). As illustrated in FIG. 11, a pixel is constituted by a single island-shaped semiconductor 20. In this pixel, an n+-type signal wiring layer 21 is formed on a substrate. Also, a metal-oxide semiconductor (MOS) transistor including a p-type semiconductor layer 22, insulating films 23a and 23b, and gate conductive electrodes 24a and 24b is formed in an outer periphery portion of the island-shaped semiconductor 20 that is in contact with the n+-type signal wiring layer 21. The gate conductive electrodes 24a and 24b are ring-shaped so as to surround the island-shaped semiconductor 20 and are electrically connected to each other. Furthermore, in the outer periphery portion of the island-shaped semiconductor 20, a photodiode that is made up of the p-type semiconductor layer 22 and n-type semiconductor layers 25a and 25b and that stores charges generated through exposure to light is formed so as to be in contact with the MOS transistor. Also, a junction transistor is formed in which the p-type semiconductor layer 22 in this photodiode serves as a channel, a p+-type semiconductor layer 26 that is in contact with pixel selection lines 27a and 27b formed on the photodiode serves as a source, and the p-type semiconductor layer 22 near the n+-type signal wiring layer 21 serves as a drain.
Also, the gate conductive electrodes 24a and 24b are electrically connected to reset gate terminals GRSL and GRSR, the p+-type semiconductor layer 26 is electrically connected to a pixel selection wiring terminal YL, and the n+-type signal wiring layer 21 is electrically connected to a signal wiring terminal XL.
A basic operation of this solid-state imaging device includes: a “signal charge storage operation” for storing signal charges (in this case, free electrons) generated through exposure to light in the photodiode made up of the p-type semiconductor layer 22 and the n-type semiconductor layers 25a and 25b; a “signal current readout operation” for modulating a source-drain current flowing between the p-type semiconductor layer 22 near the n+-type signal wiring layer 21 and the p+-type semiconductor layer 26 electrically connected to the pixel selection lines 27a and 27b in accordance with the channel width of the junction transistor that increases/decreases on the basis of a photodiode voltage (gate voltage) based on signal charges stored in the photodiode, and reading out the modulated current as a signal current; and a “reset operation” for discharging, after the signal current readout operation, the signal charges stored in the photodiode via the n+-type signal wiring layer 21 serving as a reset drain, by applying an ON voltage (positive voltage) to the gate conductive electrodes 24a and 24b of the MOS transistor.
In this pixel structure, the n+-type signal wiring layer 21 has a function of a signal current readout drain of the junction transistor and a function of a reset drain for discharging signal charges stored in the photodiode via the MOS transistor made up of the p-type semiconductor layer 22, the insulating films 23a and 23b, and the gate conductive electrodes 24a and 24b. 
FIG. 12A is a time chart illustrating a waveform ΦRG of a voltage applied to the reset gate terminals GRSL and GRSR, a waveform ΦYL of a voltage applied to the pixel selection wiring terminal YL, and a waveform ΦXL of a voltage applied to the signal wiring terminal XL in the above-described MOS transistor.
As illustrated in FIG. 12A, the signal current readout operation is performed by setting, for example, ΦRG=VL, ΦYL=VH, and ΦXL=VL, in which VH represents a high-level voltage and VL represents a low-level voltage, in a signal current readout period (ON period of a signal current readout pulse) TRO. The reset operation for discharging signal charges stored in the photodiode is performed by setting, for example, ΦRG=VH, ΦYL=VL, and ΦXL=VH, in a reset period (ON period of a reset pulse) TRS that follows the signal current readout period TRO. The signal charge storage operation is performed by setting, for example, ΦRG=VL, ΦYL=VL, and ΦXL=VL, in a signal charge storage period TS that follows the reset period TRS. A still image capturing operation is basically made up of one reset operation, one signal charge storage operation, and one signal current readout operation. Also, a moving image capturing operation is performed by repeating the reset operation, signal charge storage operation, and signal current readout operation for individual pixels.
A plurality of pixels, each being the pixel illustrated in FIG. 11, are two-dimensionally arranged in a pixel region of the solid-state imaging device. In the individual pixels, the signal wiring terminals XL and the pixel selection wiring terminals YL thereof are electrically connected to an X-direction (horizontal-direction) scanning circuit and a Y-direction (vertical-direction) scanning circuit disposed around the pixel region. In the pixel region, the individual pixels are sequentially scanned and selected on an XY matrix by the X-direction scanning circuit and the Y-direction scanning circuit, so that pixel signals are read out. In the pixel signal current readout operation, one horizontal pixel column in the X direction is read out, and then one horizontal pixel column adjacent thereto in the Y direction is read out. This operation is repeated, whereby all the pixel signals in the pixel region are read out.
FIG. 12B is a time chart illustrating a horizontal pixel signal current readout period THR1, a horizontal pixel signal current readout period THR2, . . . , and a horizontal pixel signal current readout period THRn.
As illustrated in FIG. 12B, a plurality of horizontal pixel signal current readout periods THR2, . . . , and THRn are set after one horizontal pixel signal current readout period THR1. Also, horizontal blanking periods THB1, THB2, . . . , and THBn are set between the respective horizontal pixel signal current readout periods THR1, THR2, . . . , and THRn. In the case of capturing a still image, the operation ends in one frame period from the period THR1 to the period THRn. In the case of capturing a moving image, the operation in one frame period is repeated a plurality of times.
Referring to FIG. 12B, in one frame period (horizontal pixel signal current readout periods THR1, THR2, . . . , and THRn), a signal current readout operation is performed by the junction transistor. In the solid-state imaging device having the pixel configuration according to the related art illustrated in FIG. 11, the n+-type signal wiring layer 21 serves as both the signal current readout drain and the reset drain for discharging signal charges stored in the photodiode. Thus, a signal current readout operation and a reset operation of signal charges stored in the photodiode cannot be performed at the same time.
Also, control of a shutter period is performed by changing the signal charge storage period TS, which is a signal charge readout period between the reset period TRS and the signal current readout period TRO.
In the solid-state imaging device having the pixel configuration according to the related art illustrated in FIG. 11, the n+-type signal wiring layer 21 serves as both the signal current readout drain of the junction transistor and the reset drain for discharging signal charges stored in the photodiode. Thus, in the MOS transistor made up of the p-type semiconductor layer 22, the insulating films 23a and 23b, and the gate conductive electrodes 24a and 24b, a low-level voltage VL is applied to the gate conductive electrodes 24a and 24b of the MOS transistor in the signal charge storage period TS so that the signal charges stored in the photodiode do not leak into the n+-type signal wiring layer 21. Accordingly, as illustrated in FIG. 13, in a photoelectric conversion characteristic representing the relationship between a light intensity L (the amount of incident light) to which the pixel is exposed and an output voltage Vout, the output voltage Vout monotonically increases in accordance with an increase in the light intensity L and is saturated in a certain level (saturation output level Vout1) at a light intensity L1. In this case, it is necessary to increase the area of the photodiode by extending the length of the island-shaped semiconductor forming a pixel or to increase a drive voltage in order to expand the dynamic range represented by the ratio between a noise level and the saturation output level Vout1. If the length of the island-shaped semiconductor is extended, a deep portion from a silicon pillar forming the island-shaped semiconductor 20 needs to be precisely processed, and thus it becomes difficult to manufacture the solid-state imaging device. Furthermore, an increase in drive voltage causes an increase in power consumption, which is undesirable.
Also, in the solid-state imaging device illustrated in FIG. 11, the n+-type signal wiring layer 21 serves as both the signal current readout drain of the junction transistor and the reset drain for discharging signal charges stored in the photodiode. Thus, when a signal current readout operation by the junction transistor is being performed in one pixel connected to a certain signal line via the n+-type signal wiring layer 21, a reset operation of discharging the signal charges stored in the photodiode cannot be performed in another pixel connected to the same signal line. This decreases the degree of freedom for changing the signal charge storage period TS, which is a signal charge readout period between the reset period TRS and the signal current readout period TRO, so that the controllability of a shutter period degrades. Here, a shutter operation can be performed at higher speed as the signal charge storage period TS is shorter.
Also, in the solid-state imaging device illustrated in FIG. 11, readout of a signal current by the junction transistor is performed by applying a high-level voltage VH to the p+-type semiconductor layer 26 electrically connected to the pixel selection lines 27a and 27b via the pixel selection wiring terminal YL and by applying a low-level voltage VL to the n+-type signal wiring layer 21 electrically connected to the signal line via the signal wiring terminal XL. In this case, a pn diode formed of the p-type semiconductor layer 22 serving as a channel and the n+-type signal wiring layer 21 is brought into a forward bias state. Thus, in order to operate the junction transistor in a forward current condition with a sufficiently low resistance, it is necessary to apply a voltage of at least 0.7 V or more between the p+-type semiconductor layer 26 electrically connected to the pixel selection wiring terminal YL and the n+-type signal wiring layer 21 so that the forward resistance of a PN junction is sufficiently low. In this case, drive is performed on a higher-voltage side by 0.7 V with respect to the voltage that is necessary for operating an ordinary junction transistor having no PN junction. This is undesirable in terms of decreasing power consumption of the solid-state imaging device.